----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    17:16:36 08/20/2014 
-- Design Name: 
-- Module Name:    Decoder1 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Decoder1 is
    Port ( clk_in : in  STD_LOGIC;
           ce_in : in  STD_LOGIC;
           data_in : in  STD_LOGIC_VECTOR (1 downto 0);
           data_out : out  STD_LOGIC_VECTOR (1 downto 0));
end Decoder1;

architecture Behavioral of Decoder1 is

begin

process (data_in)
begin
	case data_in is
		when "00" => data_out <= "10";		
		when "01" => data_out <= "01";		
		when "10" => data_out <= "00";		
		when "11" => data_out <= "10";		
		when others =>  data_out <= "00";
	end case;
end process;

end Behavioral;

